yosys-abc
Framework for Verilog RTL synthesis
Install
- All systems
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curl cmd.cat/yosys-abc.sh
- Debian
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apt-get install yosys - Ubuntu
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apt-get install yosys - Arch Linux
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pacman -S yosys - Kali Linux
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apt-get install yosys - Fedora
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dnf install yosys - Windows (WSL2)
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sudo apt-get updatesudo apt-get install yosys - OS X
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brew install yosys - Raspbian
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apt-get install yosys - Dockerfile
- dockerfile.run/yosys-abc
yosys
Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
qflow
Open-Source Digital Synthesis Flow
This is a complete tool chain for synthesizing digital circuits starting from verilog source and ending in physical layout for a specific target fabrication process. In the world of commercial electronics, digital synthesis with a target application of a chip design is usually bundled into large EDA software systems. As commercial electronics designers need to maintain cutting-edge performance, these commercial toolchains get more and more expensive, and have largely priced themselves out of all but the established integrated circuit manufacturers. This leaves an unfortunate gap where startup companies and small businesses cannot afford to do any sort of integrated circuit design. Qflow tries to fill this gap.